Single Phase Seven Level Stand Alone Inverter for Photovoltaic System

Authors : N. Shanmugavadivu and T. Annamalai

Keywords : Multilevel inverter (MLI), Photovoltaic (PV) System, Pulse-Width Modulated (PWM), Total Harmonic Distortion (THD)

Pages : 49-53

Abstract

Small Delay Defect Detection Using Signature Register

Authors : R. Mohanasundaram and E.K. Kavithaashri

Keywords : Very Large Scale Integration (VLSI), Large Scale Integration (LSI), Design for Testability (DFT)

Pages : 60-67

Abstract

A Low Power Asynchronous FPGA with Power Gating and LEDR Encoding

Authors : K. Naveena and N. Kirthika

Keywords : In this paper a low power Asynchronous FPGA is designed. Power gating technique is used in this paper which reduces power. The type of Power Gating used is Fine Grain Power Gating. In fine grain power gating, each LUT has its own sleep transistor and rela

Pages : 68-72

Abstract

Secure Cryptosystem for Image Encryption & Decryption

Authors : P. Geetha and S. Govindaraju

Keywords : Chaos, Bb Equation, Pseudorandom Sequence, LFSR

Pages : 73-78

Abstract

VLSI Implementation of a 2x2 MIMO-OFDM System on FPGA

Authors : R. Premalatha and M. Shanthi

Keywords : MIMO-OFDM, FFT/IFFT, Channel Estimation, FPGA

Pages : 79-84

Abstract

Survey on VLSI Architecture for 2D DWT Using Lifting Scheme

Authors : G.S. Ragavi and V. Geetha

Keywords : Architecture, Discrete Wavelet Transform, Lifting, VLSI

Pages : 85-89

Abstract

A High Bit Rate Serial-Serial Multiplier

Authors : K.R. Jisha and Dr.Rajeswari Mariappan

Keywords : Serial Serial Multiplier, Asynchronous Counters, Serial Serial Algorithm

Pages : 90-94

Abstract

Comparative Analysis of Different Multiply Accumulate Architecture

Authors : P.M. Sneha Angeline and M. Shanthi

Keywords : Baugh Wooley, Critical Path Delay, Energy Per Operation

Pages : 95-99

Abstract

Performance Analysis of High Performance Adder Architectures

Authors : Dr.P.T. Vanathi, Dr.J. Ramesh, K. Revathy, R. Preethi, C. Haritha Laxmi and K. Keerthana

Keywords : 28T CMOS Adder, 10T SERF Adder,10T CLRCL Adder, 14T Full Adder ,Proposed 14T Full Adder, Power Consumption

Pages : 100-104

Abstract

Efficient Design of a Hybrid Adder Using Quantum-Dot Cellular Automata

Authors : P. Vijayalakshmi and N. Kirthika

Keywords : Hybrid Adder, QCA-Quantum-Dot Cellular Automat, Nano Electronics

Pages : 105-109

Abstract