Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

Frequency Synthesis of All Digital Phase Locked Loop Using Sub Micron Technology

S. Saravanakumar and N. Krithika

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Abstract:

All digital Phase locked loops (ADPLL) plays a major role in System on Chips (SoC).Many EDA tools are used to design such complicated ADPLLs. It operates on two modes such as frequency acquisition mode and phase acquisition mode. Frequency acquisition mode is faster compared to phase acquisition, hence frequency synthesis is performed. The CMOS technology is used to design such a complex design in Micron Technology. The frequency of the ADPLL is synthesized using feed forward compensation techniques .All the parameters of ADPLL (Power consumption, area, locking time) are obtained using 0.18μm technology. The synthesis of ADPLL with Digitally Controlled Oscillator (DCO) and modified digitally programmable delay element (DPDE) are done and it is found that ADPLL with DPDE consumes less power compared to ADPLL with DCO.

Keywords: All Digital Phase Locked Loops(ADPLL), EDA Tool, CMOS Technology, Frequency Synthesis, Digitally Controlled Oscillator(DCO), Digitally Programmable Delay Element (DPDE).

Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development

Pages: 138-142

Issue Date: February , 2012