Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

Static Power Analysis of 32nm CMOS NAND Gate using Active and Standby Leakage Current Reduction Techniques

R. Udaiyakumar, Y. Hamsavarthini and V. Kavitha

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Abstract:

As Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are scaled down to nanometer ranges, Complementary MOS (CMOS) circuit?s total Power consumption has a new definition. It is proved in the past that dynamic power consumption tends to be the dominant factor in total power consumption of a CMOS circuit. But recent nano metric CMOS circuits? power analysis works have proved that the power consumption caused by leakage current is becoming a significant contributor to the global power consumption. This fact has motivated a lot of researchers and technologists to choose leakage current minimization as their future work. The circuit is designed using 32nm Metal gate, High-K dielectric, Silicon On Insulator (SOI) Predictive Technology Model (PTM) file developed based on Berkeley Short Channel Insulated Gate MOSFET (BSIM) model equations.

Keywords: PTM, BSIM, MTCMOS, SCCMOS, FTS, SS, LECTOR

Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development

Pages: 133- 137

Issue Date: February , 2012