Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

Design of Low Power 8T SRAM Array with Improved Noise Margin

K. Anbarasi, S. Chithra and V. Sudha

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Abstract:

Static random access memory (SRAM) has been widely used as the representative memory for logic LSIs. This is because SRAM array operates fast as logic circuits operate, and consumes a little power at standby mode. array. Therefore, the good design of SRAM cell and SRAM cell array is inevitable to obtain high performance, low power, low cost, and reliable logic LSI. Various kinds of SRAM memory cell has been historically proposed, developed and used. Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large supply voltage variations. In this paper, we propose a new compact z-shape cell layout to prioritize symmetric device placement while providing high area efficiency.

Keywords: Low Supply Voltage, SRAM, Read Disturb, Static Voltage, SRAM, Read Disturb, Static Noise Margin, Write Margin

Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development

Pages: 114-118

Issue Date: February , 2012