Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

Performance Analysis of High Performance Adder Architectures

Dr.P.T. Vanathi, Dr.J. Ramesh, K. Revathy, R. Preethi, C. Haritha Laxmi and K. Keerthana

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Abstract:

Digital Signal Processing algorithms demand high speed, high throughput and low power consuming VLSI hardware. Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. To meet these demands, power consumption and propagation delay must be reduced in adder cell which is the basic building block. The existing adders such as 28T CMOS adder, 10T Static Energy Recovery (SERF) adder, 10T Complementary and Level Restoring Carry Logic (CLRCL) adder, 14T full adder have been implemented. The power consumption and delay are high for the above adders. Hence XOR and XNOR structure based 14T full adder is proposed and implemented in TANNER tool with 1.25μ and 0.18μ technology, power consumptions and delay are estimated and compared.

Keywords: 28T CMOS Adder, 10T SERF Adder,10T CLRCL Adder, 14T Full Adder ,Proposed 14T Full Adder, Power Consumption

Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development

Pages: 100-104

Issue Date: February , 2012