Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

Comparative Analysis of Different Multiply Accumulate Architecture

P.M. Sneha Angeline and M. Shanthi

---

Abstract:

The Multiplier and Accumulator (MAC) unit is used as a basic element in most of the digital signal processing application in order to perform repeated multiplication and addition. The conventional MAC architecture uses more shift and add operation at the multiplier unit which increases delay in the arithmetic operations. The main objective is to design a new multiplier and accumulator architecture to perform high speed arithmetic operation. This is done by removing the pipeline register of the accumulate adder. Multiplication and accumulation have similar delays due to the carry propagation in the second stage. The proposed 2-cycle MAC uses Baugh Wooley algorithm and sign extension in order to increase the bit density of the operands. This architecture offers an improvement in speed and reduction in energy per operation for the operand size of 16 and 32bits .The new architecture is used to create a double throughput MAC unit(DTMAC)that switch between N-bit operations and 2*N/2-bit operations which reduces power and critical path delay on the removal of final adder. The architecture is designed using VHDL.The parameters such as power, gate count and delay is compared with the conventional architecture

Keywords: Baugh Wooley, Critical Path Delay, Energy Per Operation

Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development

Pages: 95-99

Issue Date: February , 2012