Bonfring International Journal of Power Systems and Integrated Circuits

Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year

Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)

A High Bit Rate Serial-Serial Multiplier

K.R. Jisha and Dr.Rajeswari Mariappan

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Abstract:

The paper highlights a technique for serial multiplication, which completes the partial product formation in n cycles. This is accomplished by revamping the partial product formation architecture. The proposed technique effectively forms the entire partial product matrix in just n sampling cycles for an n x n multiplication instead of at least 2n cycles in the conventional serial-serial multipliers. Here an algorithm named Serial to Serial algorithm is proposed to arrive at the architecture. The algorithm helps in reducing the complexity of partial product formation and reduction . The architecture consists of a series of asynchronous 1?s counters so that the critical path is limited to only an AND gate and a D flip-flop (DFF). The use of 1?s counter to column compress the partial products preliminarily reduces the height of the partial product matrix from n to log (n + 1), resulting in a significant complexity reduction of the resultant adder tree. Using this algorithm the multiplier is designed to carry out both signed and unsigned multiplication. The latency of operation is compared with the existing carry save add and shift (CSAS) multiplier.

Keywords: Serial Serial Multiplier, Asynchronous Counters, Serial Serial Algorithm

Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development

Pages: 90-94

Issue Date: February , 2012