Bonfring International Journal of Power Systems and Integrated Circuits
Online ISSN: 2277-5072 | Print ISSN: 2250-1088 | Frequency: 4 Issues/Year
Impact Factor: 0.651 | International Scientific Indexing(ISI) calculate based on International Citation Report(ICR)
Small Delay Defect Detection Using Signature Register
R. Mohanasundaram and E.K. Kavithaashri
Abstract:
This paper presents a scan-based delay measurement technique using signature registers for small-delay defect detection. With the scaling of semiconductor process technology, performance of modern VLSI chips will improve significantly. However, as the scaling increases, small-delay defects which are caused by resistive-short, resistive-open, or resistive-via become serious problem. If small-delay defects cannot be detected in LSI screening, the chips will behave abnormally under particular operations in certain applications, and their lifetime may become very short due to the vulnerability to the transistor aging. Therefore to keep the reliability after shipping, enhancing the quality of the testing for the small-delay defect detection is an urgent need. The scan-based delay measurement technique with the variable clock generator is one of these on-chip delay measurement techniques. In this technique, the delay of a path is measured by continuous sensitization of the path under measurement with the test clock width reduced gradually by the resolution. However, it has a drawback. The measurement time of the technique depends on the time for the scan operation. These days, the gap between the functional clock and scan clock frequency increases. Therefore the measurement time becomes too long to make it practical. The flip flop reduces the required number of scan operations, which makes the measurement time practical. In this method, we choose the longer paths to detect the smaller cumulative delay due to the small delay distributed on the paths. The larger the cumulative delays, the higher the probability of the detection of the distributed small delay. Therefore the smaller delay defects which cannot be captured with the normal clock width can be captured with the appropriate smaller test clock width.
Keywords: Very Large Scale Integration (VLSI), Large Scale Integration (LSI), Design for Testability (DFT)
Volume: 2 | Issue: Special Issue on Communication Technology Interventions for Rural and Social Development
Pages: 60-67
Issue Date: February , 2012
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