An improved SAR (Successive Approximation Register) controller is proposed to overcome the problem of dead lock in a digital calibration technique which suppresses the supply voltage sensitivity of a phase-locked loop (PLL) to achieve a fast fine lock-in. In order to reduce the supply-induced jitter, the voltage-controlled ring oscillator is designed to embed an opposite-supply-sensitivity pair which overcomes the process variations by searching the optimum code. The calibration loop is turned off once the calibration is completed and hence this method consumes much less power. The proposed SAR controller consumes less timing delay of 11.436ns which enhances the speed of the system compared with the conventional method.